NEON and VFP/VFP2/VFP3 remain an optional part of the architecture. The NEON extension defines vector instructions similar to SSE or ?AltiVec and shares a register file with the VFP unit. For practical purposes it is a normal scalar floating point unit.

In spite of the name, the base VFP architecture is not well suited for vector operations. Marvell Dove) and VFPv3+NEON (Most Cortex-A8) present in current production silicon. VFP was extended over time, with VFPv2 (some Arm9 / Arm11) VFPv3-D16 (e.g. Prior to this there was no real standardized set of floating point instructions, with some vendors supplying their own coprocessors, most supplying none, and the original Arm FPU 'standard' implementation being almost entirely unused in the real world. This is now effectively the norm for modern Arm implementations although it is possible to configure Cortex-A8, Cortex-A9 and Cortex-A5 with no VFP almost all implementations do provide it. With Armv5 an optional floating point instruction set known as Vector Floating Point ( VFP) was introduced. This section provides some background information on FPUs, Arm EABI, GCC floating-point ABIs, hwcaps. It also references similar more-complete lists elsewhere. The Arm core and application list on wikipedia may be a useful reference. This page contains background on the port itself and how and why it came to be.Ī lot of modern Arm boards and devices ship with a floating-point unit (FPU) but the current Debian armel port doesn't take much advantage of it.Ī new Arm port requiring the presence of a FPU would help squeeze the most performance juice out of hardware with a FPU.Ĭurrently the Debian armhf port requires at least an Armv7 CPU with Thumb-2 and VFP3D16. What works, what doesn't, Bugs, transitions etc.ĪrmHardFloatChroot contains quick start instructions for setting up a armhf chroot.

Partial reference of SoC and supported ISAsĪrmHardFloatTodo contains all current status information.

Performance improvements and benchmarks.

Endianess, architecture level, CPU, VFP level.

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